Serial digital transmission of non-self clocking or non-return-to-zero (NRZ) binary signals requires receiving circuitry to extract timing information from the serial data to regenerate the clock. This recovered clock is used to re-time the serial data for subsequent circuitry to receive and process it synchronously. Most methods of clock recovery, especially when implemented monolithically, use phase-locked loops (PLLs). The PLL contains a voltage-controlled oscillator (VCO) which is controlled by an integrated and low pass filtered output of a phase detector. The phase detector output is representative of the phase difference between the input serial data and the recovered clock, the latter being equal to or derived from the VCO output.
The phase difference between an input NRZ data signal and a locally generated clock signal can be obtained by generating a variable control pulse signal proportional in width to that phase difference, in addition to one or more other fixed width control pulses. The control pulses are fed to control circuitry, such as a charge pump, which yields a phase detector output signal. The phase detector output signal is filtered and integrated to produce a phase error voltage signal which is then used to drive the VCO. A phase detector such as this was disclosed in U.S. Pat. No. 4,535,459 by Hogge and modified in U.S. Pat. No. 5,027,085 by DeVito to reduce phase jitter caused by variations in data density.
While the input to the VCO directly controls the frequency of the oscillator, frequency and phase are interdependent. For instance, a brief pulse in a constant input to the VCO would alter the frequency only momentarily but would subsequently result in a fixed change in the phase of the output. Therefore, the phase of the VCO output signal will only remain the same, before and after a series of changes in the VCO input signal, if the average value of those changes is zero (or equivalently if the average value of the integrated phase detector output signal does not change).
A phase detector for this application must generate phase difference information only when input data transitions occur. Ideally, the falling edge of the clock coincides with a data transition, so that the data is phase aligned for the rising edge of the clock to retime the data in the centre of the data interval. This condition ensures the most stable and reliable reading-in of the data. When it occurs there is said to be zero phase error, and the phase of the VCO output should not change. Phase jitter, which consists of spurious variations in the phase of the regenerated clock signal must therefore be minimized.
While current phase detector circuits, for example that disclosed in U.S. Pat. No. 5,027,085 by DeVito, may provide zero static phase offset, they do not provide zero phase offset in high speed applications where the input serial data itself has significant jitter (with respect to the clock) and where practical circuitry and subsequent circuitry have limited bandwidth. The result is a reduction in input jitter tolerance. It is therefore an object of the present invention to provide a phase detector circuit which provides minimal static phase offset in the presence of large input jitter, increases the input jitter tolerance, and allows for the use of circuitry with lower bandwidth and therefore with lower current consumption.